1. Field of the Invention
This invention relates to a gate drive circuit for use in a switching device of voltage drive type, such as IGBT or FET.
2. Description of the Background Art
In a conventional switching device, its gate is driven through a gate resistance by a drive IC or a drive circuit connected to a gate power source (refer to, for example, Patent Document 1).
Patent Document 1: JP-A-8-33315 (Sectors [0008] to [0011] and FIG. 6)
Such a prior-art gate drive apparatus has had the problem that a time in which the switching device shifts from OFF to ON varies greatly, depending upon the individual characteristics of elements.
Now, the variance of the ON shift time in a turn-ON period will be explained in detail by taking an IGBT as an example and together with the operation thereof, in conjunction with FIGS. 27 and 28. Incidentally, it is assumed that a load L is an inductive load, and that a current I (A) is flywheeled by the load and a diode. FIG. 27 is a diagram of the circuit arrangement of the gate drive apparatus, while FIG. 28 is a diagram for explaining the operation thereof.
When a command of ON is given by a control signal (gate control signal), a gate drive IC applies the control voltage VDD of a control power source to the gate (G) of an IGBT 1 through a gate resistance Rg and charges a gate input capacitance Cge. On this occasion, the IGBT 1 remains OFF before a gate voltage arrives at a gate threshold voltage (Vth) ([1] in FIG. 28).
When, beyond the threshold voltage Vth, a current begins to flow through the C-E path of the IGBT 1 and the gate voltage becomes a mirror voltage Vmirror, the collector current Ic of the IGBT 1 becomes the current I (A) (a period [1] to [2] in FIG. 28).
A time period in which the current turns from OFF to ON, corresponds to a time period in which the gate voltage exceeds the threshold voltage Vth and becomes the mirror voltage Vmirror, and it is expressed by the following formula:tI-ON=−CR1n(1−Vmirror/VDD)−{−CR1n(1−Vth/VDD)}
Here, variances are involved in the mirror voltage Vmirror and the threshold voltage Vth, depending upon the individual characteristics. In, for example, the IGBT of high mirror voltage, the above time period becomes long in exponential fashion, that is, switching becomes slow ([2]′ in FIG. 28).
When the charging is further continued after the gate voltage has become the mirror voltage, the voltage Vce of the IGBT 1 shifts into an ON state (a period [2] to [3] in FIG. 28).
A time period in the meantime is expressed by the following equation, by using mirror charges (Qgc) stored in a feedback capacitance (Cgc):tV-ON=Qgc×Rg/(VDD−Vmirror)
In addition, a charging current Ig to the gate in the meantime is expressed by the following equation:Ig=ΔV/Rg=(VDD−Vmirror)/Rg 
Therefore, as the mirror voltage is higher, the time period of the voltage Vce till the ON shift becomes longer (a period [2]′ to [3]′ in FIG. 28).
Besides, the charging by the mirror voltage is further required until the voltage Vce thereafter shifts completely into the ON state, and a period therefor depends upon the current Ig (a time point [4] or [4]′ in FIG. 28).
Incidentally, the mirror voltage is determined by the gate threshold voltage Vth, current amplification factor gm and output current Ic of the IGBT 1 and depends greatly upon the voltage Vth, as indicated by the following formula:Vmirror=Vth+√(Ic/gm)
Accordingly, the variance of the voltage Vth becomes the variance of the CR charging time and becomes the variance of the Ic ON-shift time (tI-ON). Besides, the variances of the voltage Vth and the factor gm become that variance of the mirror voltage, which causes the variance of the charging current and causes the variance of the charging time, so that the Vce ON-shift time (tV-ON) varies.
The relationship between an ON shift time (tON=tI-ON+tV-ON) and a loss is expressed by the following formula:
      Ploss    ⁢                  ⁢          (      on      )        =                              1          /          2                ×        Ic        ×        Vce        ×                  t                                    I              -                        ⁢            ON                          ×        f            +                        1          /          2                ×        Ic        ×        Vce        ×                  t                                    V              -                        ⁢            ON                          ×        f              =                  1        /        2            ×      Ic      ×      Vce      ×              t        ON            ×      f      Here, Vce: the voltage Vce in a steady state, Ic: the collector current after turn-ON, and f: a switching frequency.
As stated above, both the variance of the Ic ON-shift time and the variance of the Vce ON-shift time become the variance of the switching loss.
Incidentally, the influence of the variance can be lessened by making the gate resistance value Rg smaller. In an IGBT which is actually used, however, it is generally indicated that the connection of a gate resistance is indispensable so as to prevent a switching speed from rising excessively. Besides, as an EMI countermeasure, it is a general disposal to limit “dV/dt” and “dI/dt” at the time of switching.
In the prior art, therefore, the least value of the ON shift time tON is designed under the condition of the least mirror voltage, and the gate resistance at a switching speed (max) is determined. In addition, the switching speed at the greatest mirror voltage is calculated under the condition under which the gate resistance has been determined, and the switching loss must be designed on the basis of the corresponding time period. Accordingly, the variance of the loss attributed to the variance of the mirror voltage tends to become large. Incidentally, the situation of an OFF shift is the same, and a similar problem is posed.